Low-Power Phase-Locked Loop with MEMS Oscillator
Author Information
Author(s): Kira Ahmed, Elsayed Mohannad Y., Allidina Karim, Chodavarapu Vamsy P., El-Gamal Mourad N.
Primary Institution: McGill University
Hypothesis
The study investigates the design and performance of a low-power phase-locked loop (PLL) using a MEMS-based reference oscillator.
Conclusion
The proposed PLL design achieves low power consumption and high resolution, making it suitable for modern electronic applications.
Supporting Evidence
- The PLL consumes only 6.709 μW at a 1 V supply.
- The system achieves phase noises of −106.21 dBc/Hz and −135.36 dBc/Hz at 1 kHz and 1 MHz offsets, respectively.
- The proposed PFD design eliminates dead/blind zones, improving performance.
- The PLL operates with a reference frequency of 6.89 MHz and an output frequency of 110.2 MHz.
- The design is fabricated using a TSMC 65 nm CMOS process.
Takeaway
This study shows how to make a tiny, energy-efficient timing device using a special type of oscillator that doesn't waste power.
Methodology
The study involved designing and fabricating a PLL using a MEMS oscillator and testing its performance in terms of power consumption and phase noise.
Limitations
The study does not address the long-term stability of the PLL under varying environmental conditions.
Digital Object Identifier (DOI)
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